New to ESP? Start with setting up your host, then design a single-core SoC. The architecture overview below and the ESP RISC-V Summit 2019 presentation give a concise introduction to the platform. For current commands and tool versions, use the maintained guides rather than the event tutorials.
Get started
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Set up ESP
Install host packages, the Python environment, CAD tools and the processor toolchains.
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Design a single-core SoC
Configure, simulate and prototype a minimal SoC, with side-by-side AMD/Xilinx and upcoming Intel/Altera flows.
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Design a multicore SoC
Add processor tiles and the cache hierarchy, and boot Linux SMP.
Accelerator design and integration
These flows work on AMD/Xilinx targets and are implemented in the upcoming Intel/Altera port.
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Design an accelerator in RTL
Generate an accelerator skeleton and integrate hand-written Verilog, SystemVerilog or VHDL.
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Integrate a third-party accelerator
Integrate existing AXI accelerators such as NVDLA; Vortex support is under development.
High-level synthesis
These flows use AMD/Xilinx technology mappings and are not supported by the Intel/Altera DE10-Pro SX port.
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SystemC with Cadence Stratus HLS
Design, synthesize and integrate a SystemC accelerator with Stratus HLS.
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C/C++ with AMD/Xilinx Vivado HLS
Design a C/C++ accelerator with Vivado HLS and test it on FPGA.
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C/C++ with Siemens Catapult HLS
Design a C++ accelerator with Catapult HLS and the Algorithmic C libraries.
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SystemC with Siemens Catapult HLS
Design a SystemC accelerator with Catapult HLS and MatchLib.
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C/C++ with PandA Bambu HLS Coming soon
Synthesize a C/C++ dataflow accelerator with the open-source Bambu HLS tool.
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Keras, PyTorch or ONNX through hls4ml Version-sensitive
Generate a neural-network accelerator with hls4ml; external generation steps depend on tool versions.
System features
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Design a many-accelerator SoC
Combine many accelerators in one SoC and run them concurrently with the ESP API.
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Gather performance data with the ESP Monitors API
Access memory-mapped performance counters to gather statistics about SoC operation.
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Use multicast communication
Configure point-to-point multicast between accelerators.
ASIC integration
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Integrate an ASIC technology
Integrate ASIC memory macros and I/O cells, and simulate an SoC with an ASIC technology.
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Integrate ASIC memories
Wrap ASIC memory macros for ESP and generate shared-local-memory banks.
Specifications
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ESP accelerator interface specification
Signals and protocols between an accelerator and its ESP socket (PDF).
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ESP address map
Memory-mapped address layout of ESP SoCs (PDF).
Legacy material
Archived guides for workflows that are no longer part of the current ESP source tree or recommended environment.
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Dynamic partial reconfiguration Legacy
Historical AMD/Xilinx partial-reconfiguration flow.
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Docker images Legacy
Reproduce older ESP environments with the legacy Docker images.