Documentation

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1. Set up the ESP development environment
2. Design a single-core SoC, with side-by-side AMD/Xilinx and upcoming Intel/Altera flows
3. Design a multicore SoC

The ESP RISC-V Summit 2019 presentation provides a concise architectural introduction. For current commands and tool versions, use the maintained guides below rather than the event tutorials.

Accelerator integration

The following flows work on AMD/Xilinx targets and are implemented in the upcoming Intel/Altera port:

• Design an accelerator in RTL
• Integrate a third-party accelerator, including NVDLA; Vortex support is Coming soon

High-level synthesis

These flows currently use AMD/Xilinx technology mappings and are not supported by the Intel/Altera DE10-Pro SX port:

• SystemC with Cadence Stratus HLS
• C/C++ with AMD/Xilinx Vivado HLS
• C/C++ with Siemens/Mentor Catapult HLS
• SystemC with Siemens/Mentor Catapult HLS
• Keras, PyTorch, or ONNX through hls4ml — external generation steps are version-sensitive

System features

• Design a many-accelerator SoC — the architecture and API are vendor independent; the worked HLS example targets AMD/Xilinx
• Gather performance data with the ESP Monitors API
• Configure multicast communication

Legacy material

• Dynamic partial reconfiguration — archived documentation for a historical AMD/Xilinx flow that is not present in the current ESP source tree

ASIC integration

• Integrate an ASIC technology
• Integrate ASIC memories

Specifications

• ESP Accelerator Interface Specifications
• ESP Address Map