Platform support: ESP’s HLS flows currently target AMD/Xilinx FPGA technology mappings and are not supported by the Intel/Altera DE10-Pro SX flow. Use an RTL or Third-Party accelerator on that board.
What you will learn
- Implement an accelerator for Mentor Catapult HLS in SystemC
- Two different accelerator coding styles for different Matchlib Memory Modeling options + 1 coding style for bottom-up design flow.
load,compute_dataReq,compute,store_dataReqandstoreextended structure of an accelerator- Testbench
- Catapult HLS synthesis scripts
- Device driver
- User-space application
- Validation
- Integrate a new accelerator into an ESP instance and test it on FPGA
What you will need
- Prerequisites
- Equipment
- One of the supported FPGA boards (see homepage)
- (optional) An internet router
What you can read
Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
What you can contribute
The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:
-
Accelerator designs for a wide range of application domains
-
Support for more HLS tools and libraries
Check out our contributing guidelines.