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Design a Multicore SoC

Add processor tiles, caches and Linux SMP

Open the guide

Intel/Altera multicore support is an unreleased development preview. Coming soon

This video was recorded with an earlier version of ESP. Where the video and the written guide differ, follow the guide.

What you will learn

  • Generate a multicore ESP SoC with the ESP GUI and test it through the AMD/Xilinx flow, or preview the upcoming Intel/Altera FPGA flow

Multicore SoC design workflow

What you will need

  • Prerequisites
  • Equipment
    • A supported FPGA board (see FPGA targets)
    • (optional) A network router, to reach the SoC over SSH
  • (optional) Prebuilt material for AMD/Xilinx boards
    • The FPGA bitstream (top.bit) generated in the guide
    • The Linux image (linux.bin) generated in the guide
    • The bare-metal binaries (systest.bin, prom.bin) generated in the guide

What you can read

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators

Davide Giri, Paolo Mantovani, Luca P. Carloni

IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018

Paper Slides Poster

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

  • Multicore ESP with the Ariane processor
  • A bare-metal multicore test suite for the Ariane processor

See the contributing guidelines.