C/C++ Accelerator with Siemens Catapult HLS — ESP

Open the guide

Platform support: ESP's HLS flows currently target AMD/Xilinx FPGA technology mappings and are not supported by the Intel/Altera DE10-Pro SX flow. Use an RTL or Third-Party accelerator on that board.

What you will learn

Implement an accelerator for Catapult HLS in C++
- load, compute and store structure of an accelerator
- testbench
- Catapult HLS synthesis scripts
- device driver
- user-space application
- validation
Integrate a new accelerator into an ESP instance and test it on FPGA

What you will need

Prerequisites
- Set up ESP
- Design a single-core SoC
Equipment
- A supported AMD/Xilinx FPGA board (see FPGA targets)
- (optional) A network router, to reach the SoC over SSH

What you can read

Agile SoC Development with Open ESP

Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni

(Invited) IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

Paper Pitch video Video

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

Accelerator designs for a wide range of application domains
Support for more HLS tools and libraries

See the contributing guidelines.