1) Design and integration of an accelerator with ESP
For this project each student will use ESP to design one or more accelerators and to integrate them in a system-on-chip (SoC), capable of booting Linux. Then the student will evaluate the SoC both with RTL simulation and on FPGA.
To get a more practical sense of the project, you should familiarize yourself with ESP by using the resources on this website. Specifically:
Check out the ESP website Homepage including the short introductory video
Watch the 16 minutes overview video in the Documentation section
Watch the videos and read the guides of the available hands-on tutorials available in the Documentation section. Especially relevant is the “How to: design an accelerator in SystemC” guide.
Explore the rest of the website to get the full picture of the ESP project.
For your project proposal you are asked to choose which design flow you want to use to build your accelerator.
ESP offers multiple accelerator design flows. For this project you can choose to use either the Stratus HLS flow (accelerator designed in SystemC) or the Vivado HLS flow (accelerator designed in C).
Other options include designing the accelerator in RTL (Verilog, VHDL, SystemVerilog) or designing a deep learning accelerator in Keras/Pytorch/ONNX by leveraging hls4ml. These other options don’t have full support in ESP yet. It’s possible to use them, but they will require more integration effort. If you have a strong preference for these options please let the instructors now so that you can discuss logistics and feasibility. Later on in the semester these two flows will become stable. Those of you who will be done early with their first accelerator, can decide to work on a second one with the RTL or Keras/Pytorch/ONNX flows.
For your project proposal you are asked to choose what application you want to build an accelerator for. Here is the a list of benchmark suites of applications amenable for hardware acceleration. We suggest you to select your application(s) of choice from these benchmark suites.
The benchmarks above do not include deep learning applications. If you decide to work on a deep learning accelerator specified in Keras/Pytorch/ONNX, you should either build and train you own neural network model for an application of your choice (e.g. image classification on the ImageNet dataset) or you should pick an already existing neural network model. Notice that hls4ml was born for very small networks, so it does not support very large networks yet (it will soon).
Each student can propose to implement one or more accelerators with the design flows of their preference.
The proposed steps of the project for each accelerator could be the following:
Study and polish the program to be accelerated. This will be the golden model for the accelerator design.
Generate the accelerator, complete its design and test it in isolation.
Optimize the accelerator and perform a design space exploration. This step can be moved to later stages of the project.
Complete the design of the test applications: bare-metal application and the Linux user application.
Simulate the full-system RTL of an SoC with one or more instances of the accelerator
Emulate on FPGA the SoC with the bare-metal application and with the Linux user application
Each student will work in its own fork of ESP. You can choose between a public fork on GitHub or a private fork on the internal Git servers used for the class. You can setup yourself your public forks on GitHub (GitHub fork instructions) on your own, whereas the instructors will setup the private ones.
The class servers run on the Google Cloud Platform. On the servers we
pre-installed all the software that you might need while working with ESP. You
can connect to them with either SSH or with X2Go. The latter is recommended if
you want to open the graphical interface of some tools. Remember to load the
environment every time you open a new shell by running the command:
The students will have remote access to a few FPGAs provided by the instructors. The students will receive detailed instructions on how to deploy the ESP bitstreams on those FPGAs.
In addition to submit their work regularly in their Git repository, the students will deliver a project proposal, a midterm report and a final report and presentation.