Design an Accelerator in RTL

Integrate hand-written Verilog, SystemVerilog or VHDL accelerators

The Intel/Altera RTL flow is an unreleased development preview. Coming soon

What you will learn

Generate an RTL accelerator skeleton
- RTL top-level skeleton
- device driver
- bare-metal and user-space test application skeletons
Design an SoC with the accelerator and test it

What you will need

Prerequisites
- Set up ESP
- Design a single-core SoC
Equipment
- A supported FPGA board (see FPGA targets)
- (optional) A network router, to reach the SoC over SSH

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

Completing the RTL accelerator design flow
- A design template for ESP accelerators designed in RTL
- A skeleton generation script that uses the template
- More example accelerators for this flow

See the contributing guidelines.