The Third-Party flow integrates an accelerator with a 64-bit AXI4 memory master, 32-bit APB configuration slave and interrupt. It is supported by both the AMD/Xilinx flow and the unreleased Intel/Altera development flow.
Intel/Altera support and the Vortex integration are not part of a released
ESP version yet. Coming soon
What you will learn
- How the current AXI-to-NoC socket handles bursts, transfer sizes, write strobes and coherent or non-coherent memory traffic
- How to describe, wrap, compile and register a new third-party accelerator
- How to configure and prototype an SoC with third-party accelerator tiles
- How ESP integrates NVDLA and the programmable Vortex RISC-V GPGPU Coming soon
What you will need
- Prerequisites
- Equipment
- A supported FPGA board for the prototyping sections (see FPGA targets)
What you can read
Accelerator Integration for Open-Source SoC Design
IEEE Micro (Special Issue: FPGAs in Computing), 2021
Ariane + NVDLA: Seamless Third-Party IP Integration with ESP
Workshop on Computer Architecture Research with RISC-V (CARRV), 2020
What you can contribute
The ESP team welcomes external contributions and collaborations, including:
- New accelerator integrations
- Additional bus adapters
- Vortex runtime and workload support
- NVDLA runtime or network support
See the contributing guidelines.