Dynamic Partial Reconfiguration

Legacy documentation: The DPR targets, runtime API, and example described here are not present in the current ESP source tree. This page is retained as a historical reference for the earlier AMD/Xilinx flow; do not treat its commands as instructions for the current release. The most recent public DPR development work is retained on the official esp_dpr_flow_integration branch, which is separate from ESP 2026.1.0.

Read the archived guide

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What you will learn

• The historical FPGA flow used to generate partially reconfigurable SoCs in ESP
• The FPGA flow for incremental compilation of accelerators
• Test the SoC
  • Test runtime reconfiguration (swapping) of accelerators on FPGA with both bare-metal applications and Linux

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What you will need

• Prerequisites
  • How to: setup
  • How to: setup DPR environment
  • How to: design a single-core SoC
• Equipment
  • The historical guide targets the AMD/Xilinx VC707. Later VCU118 and VCU128 work is version-sensitive and lives on the DPR development branch linked above.

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What you can read

An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs
Biruk Seyoum

PAPER

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What you can contribute

The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:

• Support for a nested (fine-grained) reconfiguration flow
• Support for an improved partial-reconfiguration software runtime manager

Check out our contributing guidelines.

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