Platform support: ESP's HLS flows currently target AMD/Xilinx
FPGA technology mappings and are not supported by the Intel/Altera DE10-Pro SX
flow. Use an RTL or
Third-Party accelerator on that board.
Tutorial videos, part 1 and part 2:
This video was recorded with an earlier version of ESP. Where the video and the written guide differ, follow the guide.
What you will learn
- Generate a customized accelerator
- source code skeleton
- testbench
- Stratus HLS synthesis scripts
- device driver
- user-space application skeleton
- Implement accelerator-specific code
- computation kernel
- input and golden output
- validation
- Edit the HLS synthesis script
- Integrate a new accelerator into an ESP instance and test it on FPGA
What you will need
- Prerequisites
- Equipment
- A supported AMD/Xilinx FPGA board (see FPGA targets)
- (optional) A network router, to reach the SoC over SSH
- (optional) Prebuilt material
- The source code, testbench and Stratus HLS scripts for the MAC accelerator
- The device drivers for the MAC accelerator
- Working folders for the AMD/Xilinx VCU118 and VC707
What you can read
High-Level Synthesis of Accelerators in Embedded Scalable Platforms
(Invited) Asia and South Pacific Design Automation Conference (ASPDAC), 2016
What you can contribute
The ESP team welcomes external contributions and collaborations, including:
- Accelerator designs for a wide range of application domains
- Support for more HLS tools
- Accelerator design flows from domain-specific languages (DSLs)
- A power estimation flow
See the contributing guidelines.