The ESP Vision

ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology.

ESP provides accelerator flows for RTL, high-level synthesis (HLS), and machine learning frameworks. These design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA.

Overview

• Architecture
  • Tile-based: processor, accelerator, memory, scratchpad and I/O tiles
  • NoC-based
  • Available processors
    • 64-bit Ariane (RISC-V)
    • 32-bit Leon3 (Sparc)
    • 32-bit Ibex (RISC-V)
• Accelerator design and integration flows
  • ESP accelerator design flows
    • RTL in Verilog, SystemVerilog or VHDL
    • SystemC with Cadence Stratus HLS
    • SystemC with Mentor Catapult HLS
    • C/C++ with Mentor Catapult HLS
    • C/C++ with Xilinx Vivado HLS
    • Machine learning frameworks (e.g. Keras/Pytorch/ONNX) with hls4ml
    • Chisel
  • Third-party accelerator integration flow
    • Example: NVIDIA Deep Learning Accelerator (NVDLA)
• SoC design flow
  • Mix & match SoC floorplanning GUI
  • Automatic SoC generation
  • Full-system RTL simulation
  • Rapid FPGA prototyping
• Software support
  • Bare-metal
  • Linux SMP
• FPGA development boards
  • Xilinx Virtex UltraScale+ FPGA VCU118 and VCU128
  • Xilinx Zynq UltraScale+ MPSoC ZCU102 and ZCU106
  • Xilinx Virtex-7 FPGA VC707
  • proFPGA Virtex7 XC7V2000T FPGA
  • proFPGA Virtex Ultrascale XCVU440 FPGA
  • proFPGA Virtex UltraScale+ XCVU19P FPGA

For more information check out the documentation section!

See here some of the supported projects, tools and languages:

Publications

Overview paper:

Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020

PAPER PITCH VIDEO

The Publications page contains the complete list of publications related to ESP.

What’s new

• ESP release 2026.1.0
  • Main memory access now uses AXI, with improved AXI-NoC burst transfers
  • FPGA memory-link width is configurable
  • Dual memory tiles are enabled on the VCU118 FPGA
  • AXI support has been expanded across all supported FPGA boards
• Improved ESP GUI
  • New GUI rollout with usability fixes and configuration cleanups
• Accelerator and infrastructure updates
  • Refined Catapult SystemC and general Catapult HLS flows
  • Updated ASIC build scripts and restored EDCL compatibility with GCC 8+
  • Fixes for RTL and third-party accelerator compilation, LeakyReLU software, async FIFO reset, cache-line handling, P2P transaction flags and non-power-of-two CPU instances

Coming soon

• Integration of the open-source Vortex GPU

• Altera/Intel FPGA board support

• Support for multiple outstanding AXI transactions

• Continued AXI, third-party accelerator, ASIC and dynamic partial reconfiguration improvements