ESP

The open-source SoC platform

Design heterogeneous SoCs, end to end

ESP is an open-source research platform for heterogeneous system-on-chip design. It combines a scalable tile-based architecture, a packet-switched network on chip, accelerator integration flows, automated hardware and software generation, full-system simulation, and FPGA prototyping.

ESP design flow

ESP’s accelerator flows support hand-written RTL, high-level synthesis and third-party IP. They converge on the same SoC integration flow, which generates the hardware sockets, device-tree entries, software interfaces and build inputs needed for a complete prototype.

Development preview: the Intel/Altera DE10-Pro SX port and Vortex integration described on this site are not part of a released ESP version yet. They are marked Coming soon throughout the documentation.

Read the documentation View ESP on GitHub

Platform overview

Architecture and software

  • Tile-based processor, accelerator, memory, scratchpad and I/O architecture
  • Configurable network-on-chip topology and memory hierarchy
  • 64-bit Ariane (CVA6), 32-bit Ibex and 32-bit LEON3 processor tiles
  • Bare-metal applications and Linux SMP
  • Automated device trees, drivers and application skeletons

Accelerator flows

  • RTL accelerators in Verilog, SystemVerilog or VHDL
  • SystemC and C/C++ accelerators with Cadence Stratus HLS, Siemens/Mentor Catapult HLS or AMD/Xilinx Vivado HLS
  • Neural-network accelerators through hls4ml
  • Third-party AXI accelerators, including NVDLA; Vortex RISC-V GPGPU support is Coming soon

HLS-generated accelerator mappings currently target AMD/Xilinx FPGA technologies. The unreleased Intel/Altera flow supports RTL and Third-Party accelerators. Coming soon

FPGA targets

  • Terasic DE10-Pro SX with Intel Stratix 10 SX 280 Coming soon
  • AMD/Xilinx VC707, VCU118 and VCU128
  • proFPGA Virtex-7 XC7V2000T, Virtex UltraScale XCVU440 and Virtex UltraScale+ XCVU19P
  • AMD/Xilinx ZCU102 and ZCU106 board ports (work in progress)

The single-core tutorial presents the released AMD/Xilinx flow alongside a preview of the upcoming Intel/Altera build, programming and payload-loading flow.

Publications

The overview paper is Agile SoC Development with Open ESP, presented at ICCAD 2020. The publications page collects the broader body of ESP research.

Releases and development status

ESP release 2026.1.0 expanded AXI memory access across supported FPGA boards, improved AXI-to-NoC burst transfers, made FPGA memory-link width configurable, and enabled dual memory tiles on VCU118.

The unreleased development tree also includes:

  • Terasic DE10-Pro SX support through Quartus Prime Pro and the board’s HPS Coming soon
  • Vortex v2.2 integration with an ESP runtime backend and configurable cores, warps, threads, L2 and L3 Coming soon
  • Improved partial-write handling and AXI channel decoupling in the third-party accelerator socket
  • Updated RTL, Catapult HLS, ASIC and ESP configuration flows

See the news archive and ESP releases on GitHub for release history.