the open-source SoC platform

The ESP Vision

ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology.

ESP provides three accelerator flows: RTL, high-level synthesis (HLS), machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA.


  • Architecture
    • Tile-based: processor, accelerator, memory, scratchpad and I/O tiles
    • NoC-based
    • Available processors
  • Accelerator design and integration flows
    • ESP accelerator design flows
      • SystemC with Cadence Stratus HLS
      • C/C++ with Mentor Catapult HLS
      • C/C++ with Xilinx Vivado HLS
      • Machine learning frameworks (e.g. Keras/Pytorch/ONNX) with hls4ml
      • Chisel
    • Third-party accelerator integration flow
      • Example: NVIDIA Deep Learning Accelerator (NVDLA)
  • SoC design flow
    • Mix & match SoC floorplanning GUI
    • Automatic SoC generation
    • Full-system RTL simulation
    • Rapid FPGA prototyping
  • Software support
    • Bare-metal
    • Linux SMP
  • FPGA development boards

For more information check out the documentation section!

See here some of the supported projects, tools and languages:


Overview paper:

Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020


The Publications page contains the complete list of publications related to ESP.

What’s new

Coming soon

  • Multi-processor support for the RISC-V Ariane cores

  • Accelerator design flow in SystemC with Catapult HLS

  • Regression testing

Latest Posts

Paper accepted at MICRO 2021
Paper accepted at MICRO 2021

Our paper “Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs” will be presented in October at MICRO 2021.

Paper published in the IEEE Micro special issue on FPGA Computing
Paper published in the IEEE Micro special issue on FPGA Computing

Our paper “Accelerator Integration for Open-Source SoC Design” has been published in the IEEE Micro special issue on FPGA Computing (Jul-Aug 2021).

Twitter Posts