ESP

the open-source SoC platform


The ESP Vision

ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology.

ESP provides three accelerator flows: RTL, high-level synthesis (HLS), machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA.

Overview

  • Architecture
    • Tile-based architecture: processor, memory and accelerator tiles
    • NoC-based
    • Available processors
  • Accelerators
    • ESP accelerators
      • Cadence Stratus HLS flow
      • Xilinx Vivado HLS flow (NEW)
      • Chisel flow
    • Third-Party Accelerators (NEW):
      • NVIDIA Deep Learning Accelerator (NVDLA)
  • Design Flows
    • Seamless accelerator design flows:
    • Mix & match floorplanning GUI
    • Rapid FPGA prototyping
  • Hardware and software support

For more information check out the documentation section!


See here some of the supported projects, tools and languages:


What’s new

  • Support for Vivado 2019.2 and Modelsim SE 2019.2

  • Support for Xilinx board VCU128

  • Fully-automated integration of machine-learning accelerators with hls4ml
  • Support for proFPGA quad Virtex UltraScale Prototyping System, including up to 4 memory channels

Coming soon

  • Multi-processor support for the RISC-V Ariane cores

Latest Posts

NVDLA+Ariane with ESP at CARRV 2020
NVDLA+Ariane with ESP at CARRV 2020

Our paper Ariane+NVDLA: Seamless Third-Party IP Integration with ESP will appear at CARRV.

Released ASPLOS 2020 tutorial
Released ASPLOS 2020 tutorial

The material for the ASPLOS 2020 tutorial is available on the tutorial page under the Program section.

Twitter Posts