ESP

the open-source SoC platform


The ESP Vision

ESP is an open-source research platform for heterogeneous system-on-chip design that combines a flexible tile-based architecture and a modular system-level design methodology.

ESP provides three accelerator flows: RTL, high-level synthesis (HLS), machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA.

Overview

  • Architecture
    • Tile-based architecture: processor, memory and accelerator tiles
    • NoC-based
    • Available processors
  • Accelerators
    • ESP accelerators
      • Cadence Stratus HLS flow
      • Xilinx Vivado HLS flow (NEW)
      • Chisel flow
    • Third-Party Accelerators (NEW):
      • NVIDIA Deep Learning Accelerator (NVDLA)
  • Design Flows
    • Seamless accelerator design flows:
    • Mix & match floorplanning GUI
    • Rapid FPGA prototyping
  • Hardware and software support
    • Linux SMP
    • FPGA development boards
      • Xilinx Virtex UltraScale+ FPGA VCU118
      • Xilinx Virtex-7 FPGA VC707
      • proFPGA quad Virtex7 Prototyping System

For more information check out the documentation section!



What’s new

  • Integration of the NVIDIA Deep Learning Accelerator (NVDLA)

  • Support for Ubuntu 18.04

  • Support for Vivado HLS accelerators

Coming soon

  • Multi-processor support for the RISC-V Ariane cores

  • Support for Digilent Genesys2 FPGA board

  • Regression testing

  • Automatic integration of accelerators generated with hls4ml from Keras/Tensorflow and Pytorch

Latest Posts

Upcoming talk on ESP at the RISC-V Summit
Upcoming talk on ESP at the RISC-V Summit

Join Luca in San Jose on December 11th for a talk about ESP at the RISC-V Summit: Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform.

Integration of the NVIDIA Deep Learning Accelerator
Integration of the NVIDIA Deep Learning Accelerator

It is now possible to create an ESP instance with one or multiple accelerator tiles hosting the NVIDIA Deep Learning Accelerator (NVDLA). This feature is available with RISC-V only, when selecting Ariane for the ESP processor tile.

Twitter Posts