the open-source SoC platform

Coming up: New overview paper on ESP to be presented at ICCAD 2020 on November 3rd (preprint)

The ESP Vision

ESP is an open-source research platform for heterogeneous system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology.

ESP provides three accelerator flows: RTL, high-level synthesis (HLS), machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable full-system prototyping on FPGA.


  • Architecture
    • Tile-based architecture: processor, memory and accelerator tiles
    • NoC-based
    • Available processors
  • Accelerators
    • ESP accelerators
      • Cadence Stratus HLS flow
        • Mentor Catapult HLS flow
      • Xilinx Vivado HLS flow
      • Chisel flow
    • Third-Party Accelerators:
      • NVIDIA Deep Learning Accelerator (NVDLA)
  • Design Flows
    • Seamless accelerator design flows:
    • Mix & match floorplanning GUI
    • Rapid FPGA prototyping
  • Hardware and software support

For more information check out the documentation section!

See here some of the supported projects, tools and languages:


Overview paper:

Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni. “Agile SoC Development with Open ESP.” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020.

The Publications page contains the complete list of publications related to ESP.

What’s new

Coming soon

  • Multi-processor support for the RISC-V Ariane cores

  • Accelerator design flow in SystemC with Catapult HLS

  • Regression testing

Latest Posts

Upcoming tutorial at MICRO 2020
Upcoming tutorial at MICRO 2020

We will present a tutorial on ESP at MICRO 2020.

Upcoming talk at VLSISoC 2020
Upcoming talk at VLSISoC 2020

Professor Carloni will give a talk titled “Scalable Open-Source System-on-Chip Design” at the VLSISoC conference on October 7th, 2020.

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