Design a Single-Core SoC

Open the guide

This video was recorded with an earlier version of ESP. Where the video and the written guide differ, follow the guide.

What you will learn

• Generate a minimal ESP SoC with the ESP GUI
• Choose a processor: Ariane, Ibex or LEON3, or the OpenHW CVA6 core on the development branch Coming soon
• Use the AMD/Xilinx build and programming flow, or preview the upcoming Intel/Altera flow
• Test the SoC
  • Run full-system RTL simulation
  • Test on FPGA with bare-metal software and with Linux
  • Connect to the SoC with SSH

What you will need

• Prerequisites
  • Set up ESP
• Equipment
  • A supported FPGA board (see FPGA targets)
  • (optional) A network router, to reach the SoC over SSH
• (optional) Prebuilt material for AMD/Xilinx boards
  • The FPGA bitstream (top.bit) generated in the guide
  • The Linux image (linux.bin) generated in the guide
  • The bare-metal binaries (systest.bin, prom.bin) generated in the guide

What you can read

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

• Support for more FPGA targets
• A power estimation flow
• An ASIC back-end flow

See the contributing guidelines.