ISCA 2024 tutorial
The ESP Approach to Agile Chip Design
Latest update: 2024-06-20
Logistics
Tutorial date: Saturday June 29 or Sunday June 30, 2024.
Tutorial venue: Hilton Buenos Aires.
Tutorial registration: Instructions.
Preliminary setup: Instructions.
Hands-on tutorial steps: (COMING SOON!).
If you are interested in attending this tutorial, please be sure to sign up for it when registering for ISCA.
Tutorial Overview
Energy-efficient, high-performance computing requires the integration of specialized accelerators with general-purpose processors. Designing such systems, however, imposes a difficult set of challenges, particularly for small teams. Integrating and verifying many components, potentially designed by different teams with different tools, into a single SoC is already a difficult task. Arriving at functional FPGA prototypes and real silicon implementations further increases the complexity exponentially. In this tutorial, we present ESP, an open-source platform to support research on the design and programming of heterogeneous SoC architectures. By combining a scalable, modular, tile-based architecture with a flexible system-level design methodology, ESP simplifies the design of individual accelerators and automates their hardware/software integration into complete SoCs. This tutorial focuses on recent developments to ESP for ASIC design, which are backed by real silicon implementations.
In the first part of the tutorial, attendees will be given a hands-on introduction to ESP, showing them how to design a new custom accelerator for ESP, how to generate an FPGA bitstream for a complete SoC featuring that accelerator, and how to deploy software applications that invoke the accelerator. We will also demo new extensions to the ESP network-on-chip that enhance the flexibility of on-chip communication for many-accelerator SoCs.
The next section of the tutorial will focus on ASIC design of ESP SoCs. We will leverage an open-source process design kit (PDK) to integrate memories, pads, and clock generators into the design. Next, we will show how to perform functional verification of the SoC – both with the RTL design and synthesized netlists – and describe how the same tests can be leveraged to perform bring-up on the fabricated silicon thanks to our provided test infrastructure. Finally, we will show how to prepare the design for synthesis and place and route and discuss some best practices for physical design based on our experience with two complex silicon implementations.
The last part of the tutorial focuses on the design and integration of embedded FPGAs into ESP-based SoCs. We first demonstrate the design and tool flow to generate the RTL of the custom FPGA, leveraging the open-source OpenFPGA framework to automate this process. We then describe the architectural modifications and new components designed to enable the integration of an FPGA fabric inside ESP alongside CPUs, memory, I/O peripherals, and fixed-function accelerators. Finally, we demonstrate the compilation and execution flow of applications targeting the embedded FPGA inside ESP.
For more information check out the Github release, the Publications page and the Tutorials and talks page on this website.
Preliminary setup
If they wish, participants have the opportunity to try the parts of the tutorial that don’t require licensed CAD tools or FPGAs. Doing so requires to go through some preliminary setup before the beginning of the tutorial. There are two options:
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use the Docker image for the ESP tutorial: instructions.
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install on your machine the packages and tools required by ESP: instructions.
Program
| Time | Agenda | Material |
|---|---|---|
| Introduction | ||
| 9:00-9:20 am | Overview | Slides Video |
| 9:20-9:40 am | How to: Design an accelerator with SystemC and Stratus HLS | Tutorial |
| 9:40-10:00 am | How to: Accelerator integration, FPGA prototyping, and software development | Tutorial (single-core) Tutorial (multi-core) |
| 10:00-10:20 am | Break | |
| Deplyoing Software Applications on Many-Accelerator SoCs | ||
| 10:20-10:35 am | How to: Software development with the ESP accelerator invocation and performance monitors APIs | Tutorial (many-accelerator) Tutorial (monitors-api) Paper |
| 10:35-10:50 am | Case Study: Complex data dependencies on the Wide-Area Motion Imagery (WAMI) application | Paper |
| ASIC Design with ESP | ||
| 10:50-11:05 am | Case Study: Prior ESP Chip Designs | ESP at ISSCC ESP’s First Chip |
| 11:05-11:25 am | How to: prepare an SoC for ASIC design with the Skywater PDK | Tutorial |
| 11:25-11:35 am | How to: Verify and test an ESP ASIC | ASIC Methodology Paper |
| Supporting Embedded FPGAs in ESP | ||
| 11:35-12:00 pm | Case Study: eFPGA integration in the ESP archietcutre with OpenFPGA | OpenFPGA |
| 12:00-12:20 pm | How to: accelerator compilation, bitstream generation, and programming flow for eFPGA-SoCs | |
| 12:20-12:30 pm | Teaching with ESP and concluding remarks | Paper Material |
Video recording
(COMING SOON!)
Team
System-Level Design (SLD) group at Columbia University, New York.
Speakers
Luca P. Carloni is professor and chair of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the MS and PhD degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His research interests include heterogeneous computing, system-on-chip platforms, embedded systems,and open-source hardware. He coauthored over one hundred and seventy refereed papers. Luca received the NSF CAREER Award, the Alfred P. Sloan Research Fellowship, and the ONR Young Investigator Award. He is an IEEE Fellow.
Kuan-Lin Chiu is a PhD student in Computer Science at Columbia University. He received his BS degree in Engineering Science and Ocean Engineering from National Taiwan University and MS degree in Electrical and Computer Engineering from University of California, Los Angeles. His research interests include system-level design methodologies for heterogeneous system-on-chip platforms, focusing on hardware accelerators and on-chip data movement for image processing and machine learning.
Biruk Seyoum received his PhD from the Real-Time Systems (ReTiS) Laboratory of Scuola Superiore Sant’Anna. He is currently a post-doctoral research scientist in the System-Level Design group at Columbia university. His research interests include design and implementation of heterogeneous architectures for reconfigurable platforms, design tools and applications for dynamic partially reconfigurable platforms, and FPGA-based deep neural network acceleration.
Joseph Zuckerman is a Computer Science PhD candidate at Columbia University, working in the System-Level Design group. His research interests include agile design methodologies, novel architectures, and runtime optimization of heterogeneous systems-on-chip. He is the recipient of an NSF Graduate Research Fellowship and previously completed his bachelor’s degree in electrical engineering at Harvard University in 2019. Joseph currently leads the development of ESP.