Tutorial at ASPLOS 2020
The ASPLOS 2020 event in Lausanne has been cancelled and replaced by a virtual conference. During the upcoming week (March 16th-20th) we will release the material for the ESP tutorial, which consists of a set of hands-on video tutorials and written guides. We will post all the material in the Program section of this page, under Material. Part of the material is already available.
The ASPLOS organizers created a Slack workspace for the conference open to everyone. Here is an invite link. We have a channel called #tutorial-esp-soc-platform on the ASPLOS 2020 Slack. We will be monitoring the channel closely, so feel free to join the channel, ask questions, start discussions or provide feedback.
Tutorial date: March 17th, 2020 (in the morning)
Tutorial venue: the Swiss Tech Convention Center
Tutorial registration: The discounted early registration is available until February 24, 2020.
What is ESP?
The system-on-chip (SoC) lies at the core of modern computing systems for a variety of domains, from embedded systems to data centers. In any given domain, the success of a particular SoC architecture is bound to the set of special-purpose hardware accelerators that it features next to general-purpose processors. This heterogeneity of SoC components brings new challenges to hardware designers as well as software programmers.
This tutorial illustrates ESP, a new open-source platform to support research on the design and programming of heterogeneous SoC architectures. By combining a scalable modular architecture with a system-level design methodology, ESP simplifies the design of individual accelerators and automates their hardware/software integration into complete SoCs. Furthermore, ESP enables rapid prototyping of these architectures on FPGA-based infrastructures. With ESP, researchers in architectures, compilers, and operating systems can evaluate new ideas by running complex user applications on top of a complete Linux-based software stack and invoke many different hardware accelerators to process very large data sets from main memory.
The Publications page on this website contains the list of publications on ESP.
On the Tutorials and talks page on this website you can find the list of talks on ESP .
The tutorial starts with a complete overview of the ESP project and includes a series of “How to” sections, each introducing a set of main features of ESP in a practical way. All the tutorial material is linked in the table below.
|Overview on the ESP project||Slides, Video|
|How to: design and deploy on FPGA a multi-core SoC with ESP||Tutorial (singlecore), Tutorial (multicore)|
|How to: design and integrate accelerators in SystemC with ESP||Tutorial|
|How to: design and integrate accelerators in C/C++ with ESP||Tutorial|
|How to: design and integrate accelerators in Keras/Pytorch/ONNX with ESP||Tutorial|
|How to: design and deploy on FPGA a many-accelerator SoC with ESP, deploy many-accelerator applications, and reconfigure cache coherence||Tutorial|
Luca P. Carloni is Professor of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree in Electronics Engineering from the University of Bologna and the MS and PhD degrees in Electrical Engineering and Computer Sciences from UC Berkeley. His research interests are in system-on-chip platforms and distributed embedded systems. He coauthored over one hundred and forty refereed papers. Luca received the NSF CAREER Award, the ONR Young Investigator Award, and an Alfred P. Sloan Research Fellowship. In 2013, Luca served as general chair of Embedded Systems Week. Luca is an IEEE Fellow.
Davide Giri is a PhD student in Computer Science at Columbia University. He received the MS degree in electronic engineering from Politecnico di Torino and the MS degree in electrical and computer engineering from the University of Illinois at Chicago. His research interests include architectures and system-level design methodologies for heterogeneous system-on- chip. Davide is one of the architects of the ESP project.
Paolo Mantovani is an Associate Research Scientist at Columbia University. He earned the MS in Electronic Engineering at Politecnico di Torino and the PhD in Computer Science at Columbia University. His PhD and current research interests include architecture design and system-level methodologies for the integration and programming of heterogeneous computing platforms. Paolo contributes to the open-source hardware community as the main architect of the Embedded Scalable Platforms architecture and FPGA emulation infrastructure.