Design a Many-Accelerator SoC — ESP — Open-Source SoC Platform

Many-accelerator demonstration with the ESP monitors and run-time reconfigurable cache coherence for accelerators:

What you will learn

Create a multi-accelerator instance of ESP
Use the ESP software API to configure a multi-accelerator application
- run-time coherence reconfiguration
- concurrent execution
- point-to-point communication

Many-accelerator SoC workflow

Prerequisites
- Set up ESP
- Design a single-core SoC
Recommended
- Design a SystemC accelerator with Stratus HLS
Equipment
- A supported FPGA board (see FPGA targets)
- (optional) A network router, to reach the SoC over SSH
(optional) Prebuilt material
- Working folders for the AMD/Xilinx VCU118 and VC707
- A precompiled Linux image with the multifft example

Davide Giri, Kuan-lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni

(Best Paper Nominee) Design, Automation and Test in Europe Conference (DATE), 2020

Davide Giri, Paolo Mantovani, Luca P. Carloni

(Invited) Asia and South Pacific Design Automation Conference (ASPDAC), 2019

The ESP team welcomes external contributions and collaborations, including:

An improved user-level API for accelerator configuration and scheduling
Novel algorithms for run-time selection of the cache-coherence model in multi-accelerator applications