How to: design an accelerator in RTL
Tutorial guide:
What you will learn
- Generate RTL accelerator skeleton
- RTL skeleton
- device driver
- bare-metal and user-space test applications skeleton
- Design an SoC with the accelerator and test it
What you will need
- Prerequisites
- Equipment
- One of the supported FPGA boards (see homepage)
- (optional) An internet router
What you can contribute
The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:
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Complete the RTL accelerator design flow
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Design template for ESP accelerators designed in RTL
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Implement the skeleton generation script that leverages the template
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Add example accelerators for this flow
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Check out our contributing guidelines.