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Multicore SoC Guide

Contents

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This guide illustrates how to generate and test a multi-core ESP SoC. It shares many steps with the single-core SoC guide, which it references throughout. Complete the prerequisite guides before starting this one, as this guide builds on them without repeating their content.

Intel/Altera development preview: the DE10-Pro SX instructions are not part of a released ESP version yet. Coming soon

Note: The users have access to prebuilt material to run the tutorial on an FPGA, without executing all the previous steps. See the ‘FPGA prototyping with prebuilt material’ section at the end of this guide.

Target FPGA board

Choose the working folder for your FPGA board. The SoC configuration steps are shared; synthesis, programming and payload loading use the vendor-specific targets described in the single-core SoC guide.

AMD/Xilinx example: VC707 
cd <esp>/socs/xilinx-vc707-xc7vx485t
Intel/Altera example: Terasic DE10-Pro SX 
cd <esp>/socs/terasic-de10-pro-sx

The DE10-Pro SX port is validated with Quartus Prime Pro 19.4. Its FPGA image must include the HPS bridge, so generate the matching HPS artifacts before Quartus synthesis. See the board-specific section of the single-core guide for the exact commands.

SoC configuration

Open the ESP configuration GUI:

make esp-xconfig


Select a 3x2 or 2x3 layout and set 4 processor tiles, 1 memory tile and 1 I/O tile, then save and close. The figure below shows the GUI with a possible configuration for a quad-core ESP instance. ESP supports multi-core SoCs with Leon3, Ariane and Ibex processor tiles. Make sure the ESP caches are enabled, because they are mandatory for multi-core instances of ESP. To support multi-core operation the ESP caches implement a directory-based MESI protocol over the NoC.

ESP multicore configuration

Cache configuration

The ESP Cache hierarchy is mandatory for a multi-core SoC. See Choose the cache implementation in the single-core SoC guide for more details. Use the RTL cache implementation for the Intel/Altera flow; the SystemC cache implementation requires HLS and is currently limited to AMD/Xilinx targets.

Follow the Configure the host-to-board connection instructions in the single-core SoC guide.

FPGA prototyping

Follow the FPGA build, programming and payload instructions in the single-core SoC guide. The only difference is that before compiling Linux with the make linux command, you should enable the Linux multi-core (Linux SMP) by setting a flag in the local Makefile in the socs subfolder you’re working in.

SMP = 1

With the CVA6 processor on the dev branch, SMP = 1 selects the cva6_smp_defconfig Linux configuration. Coming soon

Note: The bare-metal “Hello ESP!” test executes on a single core. ESP provides bare-metal multicore programs, but they are outside the scope of this guide.

Once you login into Linux you can run top in the terminal to see that the Linux processes are running on all four processor cores. See an example in the image below:

Linux top running on a multicore ESP instance

FPGA prototyping with prebuilt material

Prebuilt-version notice: these archives were generated for the Git revision named in each package. They are not guaranteed to match ESP 2026.1.0. Use the source-build instructions above when working with the current release, and use an archive only with its documented revision.

Follow the Use prebuilt material instructions in the single-core SoC guide. The current prebuilt tutorial material targets AMD/Xilinx boards. Build the DE10-Pro SX image and HPS artifacts locally by following the Intel/Altera instructions instead.